1. Field of the Invention
The present invention generally relates to high performance array chips, such as random access memories, and, more particularly, to an improved decoder/driver circuit which reduces the overall chip power.
2. Description of the Prior Art
High performance array chips, such as Static Random Access Memories (SRAMs) and Dynamic Random Access Memories (DRAMs), are being fabricated in ever higher densities. Power dissipation in array word line and bit column decoder/driver circuits is a critical problem because their power dissipations can be a large portion of the total chip power. It is therefore important to minimize overall chip power in these high performance array chips.